1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a technique for improving a withstand voltage characteristic of the semiconductor device of a trench gate type.
2. Description of Related Art
In order to improve the withstand voltage characteristic of the semiconductor device, the semiconductor device in which a floating region is formed at the bottom of a gate trench (that is, a gate insulator) is known in the related art (for example, Japanese Patent Application Publication No. 2005-116822 (JP 2005-116822 A)). In the semiconductor device disclosed in JP 2005-116822 A, when the semiconductor device is turned off, two peaks of electric fields are produced at a boundary between a body region and a drift region and a boundary between the floating region and the drift region. The maximum peak value of an electric field can be limited by producing the peak of the electric field at a plurality of positions. Accordingly, withstand voltage characteristic of the semiconductor device is improved.
In the semiconductor device of this type, the position and the shape of the floating region at the bottom of the gate trench are changed according to the characteristics required for the semiconductor device. For example, there is a case where the floating region at the bottom of the gate trench is required to be formed in the vicinity of the body region in order to relax the electric field applied to the gate insulator. In such a case, the semiconductor device having a conventional structure may cause a connection between a depletion layer extending from the body region and a depletion layer extending from the floating region under a condition where a bias is not applied to the semiconductor device when the floating region is arranged in the vicinity of the body region. When these depletion layers are connected to each other, there is a possibility of an increase in ON-resistance.